The present application relates to semiconductor device fabrication, and more particularly, to the fabrication of vertical field effect transistors (FETs).
Field effect transistors (FETs) are typically formed on a substrate and include a channel region disposed between source and drain regions, and a gate configured to electrically connect the source region and the drain region through the channel region. FETs can be classified into horizontal architectures and vertical architectures. A horizontal FET has a channel region parallel to the horizontal surface of the substrate, while a vertical FET has a channel region perpendicular to the main surface of the substrate. Thus, in a vertical FET, the direction of the current flow between the source region and the drain region is normal to the main surface of the substrate. By employing a vertical device configuration, it is possible to increase packing density. Vertical FETs thus can potentially extend scaling.
Group III-V compound semiconductors possess high electron mobility and are suitable for n-type FETs. Group III-V compound semiconductor nanowires can be grown vertically from a semiconductor substrate, which makes them a good candidate for vertical FETs. However, since a high temperature epitaxy process is needed for formation of the source region and the drain region for p-type FETs, it would be desirable to grow Group III-V compound semiconductor nanowires after the high temperature source/drain epitaxy process has been performed for construction of n-type FETs.